PCB Factory: Is 14nm a "barrier" of global semiconductor technology?

circuit board manufacturers, circuit board designers and PCBA manufacturers explain to you that circuit board factories: 14nm is a "barrier" of global sEMIconductor technology?

Size reduction is a "magIC drug" to promote industrial progress. The magic spell of size reduction of 70% every two years shows no signs of delay. In 2011, it was a 22nm process, and in 2013, it should be 14nm. As we all know, size reduction is only a means. If there is no dividend due to size reduction, the industry will not blindly follow up. According to the current situation, there has been some controversy in the industry. Some people think that the cost may rise during the transition from 28nm to 22nm, which is a normal phenomenon in the process of industrial transition.

There may be less than 10 enterprises in the global semiconductor industry that can continue to track 14nm process nodes. Obviously, NAND flash memory and CPU manufacturers and a number of FPGA manufacturers are the leading enterprises in the semiconductor industry. However, OEM manufacturers, such as TSMC, usually lag behind a generation due to MARKet demand. This does not mean that the OEM model will definitely lag behind IDM, because the market economy needs to balance technical capabilities and costs. Recently, Altera, such as FPGA, skipped TSMC and directly sought to cooperate with Intel to develop 14nm FPGA, reflecting the complexity of the market.

As we all know, size reduction is only a means. It seems that the industry is betting on FinFET 3D process and EUV lithography to continue to move forward. In the long run, the development of integrated circuit industry always balances performance, cost and power consumption, and the market makes the final choice. The cost shall be reduced as much as possible on the premise of maintaining the performance, and the power consumption shall be reduced as much as possible on the premise of maintaining the performance and cost.

Dean Freeman, an analyst at Gartner, a market research organization, said recently that the current situation faced by the semiconductor industry was very SIMilar to the situation in the 1980s, when the industry began to gradually use CMOS technology to manufacture memory and logIC chips in order to get rid of the development bottleneck it faced, thus ushering in a new era in the semiconductor industry. Whether the current 3D process using FinFET will produce the same halo is worth looking forward to.

For 22nm/16nm process, the industry believes that there are many transistor structures to choose from, including III-V family channel technology, bulk silicon technology, FinFET solid transistor technology, FD-SOI fully depleted planar transistor technology, and multi gate solid transistor technology. However, according to the current analysis, since 14nm (including 14nm), the use of FinFET 3D structure process may become the mainstream technology.

At this stage, there are two technologies competing with each other: one is the three gate transistor technology with FinFET structure that Intel said it would start to use in the 22nm process. The other is that companies such as IBM and STF Semiconductor said they would consider using FD-SOI or FD-UT SOI full depletion technology at the 22nm process node. IBM has demonstrated an ultra-thin FD-UT SOI process in the past two years. The advantage of this process technology is that it is still based on the traditional planar transistor structure. However, the silicon layer thickness of SOI in this process is very thin, between 5nm and 6nm, which facilitates the formation of a fully depleted (FD) structure and can significantly reduce the impact of short channel effect (SCE).

Although the process and technology routes adopted by Intel and IBM are different, the market economy is fair. Both sides will show their strengths and make trade-offs according to market demand. Circuit board manufacturers, circuit board designers and PCBA manufacturers explain to you that circuit board factories: 14nm is a "barrier" of global semiconductor technology?