Gigabit serial I/O technology has excellent performance, but these superior performance needs conditions to ensure, that is, excellent signal integrity. For example, one PCB vendor reported that when they first tried to use a high-speed, gigabit level serial design for a specifIC application, the failure rate was 90%. In order to improve the success rate, we may need to carry out SIMulation and adopt more complex new bypass circuits.

The GTP performance of Spartan-6 FPGA depends on the signal integrity of, and the following factors need to be taken into account: the stack structure of the board, the Layout of components, and the signal routing.

Pcb design process

Power supply and stack

For GTP transceiver of Spartan-6 FPGA, the stack can be divided into two groups, PCB power distribution layer and signal routing layer. The power layer is used to connect the MGTACC, MGTAVCCPLL, MGTAVTTTX and MGTAVTTRX power pins of GTP.

In the stack, the ground plane layer transmission signal line provides a signal return path. At the same time, since there is a shielded plane between the two signal layers, the problems that need to be considered in the routing of adjacent layers can be ignored when routing PCB signals, and more signal paths are provided.

The power supply layer of GTP should be closely adjacent to the ground plane to increase coupling effect. The ground plane can provide shielding for the power supply plane of GTP. The shielding power supply plane is from the noise interference caused by the signal of the upper or lower layer.

In fact, from another point of view, when the power supply noise appears in the high-frequency range, with the increase of frequency, it is increasingly difficult to find a capacitor that can cover this frequency range to achieve filtering effect, until it is impossible to find such a capacitor. As the capacitance value decreases, the related stray inductance and package resistance do not change correspondingly, so the frequency response will not change too much. In order to achieve better power distribution at high speed, we need to use the power layer and stratum to construct our own capacitance. In order to achieve our goal more effectively, we usually need to use adjacent power layers and strata.

The connection between GTP power pin and power distribution network plays a key role in GTP performance. PDN and FPGA need low impedance and low noise connection. The maximum noise tolerance of the FPGA GTP power supply is 10mVpp. In the range of 10KHz to 80MHz, a SMAll plane can be used for the power supply. This small power plane should not cover the area of the SelectIO interface.

PCB design capacitor placement

In addition to the capacity value of bypass capacitor, another important aspect to be considered is the placement of capacitor.

The general rule is that the larger the capacitance value, the less strict the placement requirements. If the capacitance value is small, the capacitance should be as close to the power and ground pins as possible. One method that can be used is to remove the wiring and vias of unused general-purpose IO, thus making room for bypass capacitors

The location of the GTP power division area and the location of the GTP filter capacitor.

Signal routing

GTP signal routing and SelectIO signal routing should be avoided at adjacent layers, and their respective return paths should also be kept separate, including via.

It is important to keep a certain distance between differential line pairs and between differential lines and other lines. The general rule is that the distance between adjacent line pairs should be at least 5 tiMES the distance between two lines in the line pair.

The differential line of gigabit signal shall avoid changing the routing layer as much as possible. If cross layer transmission is necessary, special care should be taken. First, you must provide a complete return path. Therefore, we must couple the reference layer of layer A and the reference layer of layer B. The ideal situation is that both reference layers are strata. In this case, the return path can be realized by placing another via connecting the two reference layers near the layer transfer via. If the reference layer is different (one is the stratum, the other is the power layer), it is necessary to

Square place 0.01 μ F to connect two reference layers, reducing the impedance of the return path.

There may be many problems in the PCB design process, but as long as you carefully do every detail, you can design a good PCB schematic.